module EPM240
   (
    input wire clk,
    input wire in1,
    input wire in2,
    input wire in3,
    input wire in4,
    output wire out1,
    output wire out2,
    output wire out3,
    output wire out4
    );

localparam    clk_freq = 50_000_000,
            inter_coarse_freq = 10_000,   
            inter_coarse_value = clk_freq / inter_coarse_freq,
            period_coarse_freq = 200_000,
            period_coarse_value = clk_freq / period_coarse_freq,
            start_pulse_value = period_coarse_value / 8;
   
reg[15:0]   cnt = 0;   
   
reg[8:0]      d1 = 0,
            d2 = 72,
            d3 = 72;
           
reg[0:0]      fb_l = 0,
            fb_l_pre = 0,
            fb_r = 0,
            fb_r_pre = 0,
            channel_1 = 0,
            channel_2 = 0,
            d2_inc_en = 0,
            d3_dec_en = 0;
//----------
always @ (posedge clk)   
begin
//----------   
   fb_l = in1;
   fb_r = in2;
//----------   
   if (cnt != (inter_coarse_value - 1)) cnt = cnt + 1;
   else cnt = 0;
//----------   
   if (d2_inc_en == 1) d2 = d2 + 1;
   if (d3_dec_en == 1)
      begin
         if (d3 == 0)
            begin
               d3_dec_en = 0;
               if (fb_l == 0) channel_2 = 0;
               else channel_2 = 1;
            end
         else d3 = d3 - 1;
      end
//----------| start | ----------   
   if (cnt == 0) channel_1 = channel_1 ^ 1;
   if (channel_1 == 0) channel_2 = 0;
//----------| d2 & d3 | ----------
   if ((fb_l_pre == 0)&&(fb_l == 1))   // fb_l __/--
   begin
      d3_dec_en = 1;
      d2_inc_en = 1;
      d3 = d2 - d1;
      d2 = 0;
      fb_l_pre = fb_l;
   end
   
if ((fb_r_pre == 0)&&(fb_r == 1))      // fb_r __/--
   begin
      d2_inc_en = 0;
      fb_r_pre = fb_r;
   end
   
if ((fb_l_pre == 1)&&(fb_l == 0))      // fb_l --\__
   begin
      d3_dec_en = 1;
      d2_inc_en = 1;
      d3 = d2 - d1;
      d2 = 0;
      fb_l_pre = fb_l;
   end
   
if ((fb_r_pre == 1)&&(fb_r == 0))      // fb_r --\__   
   begin
      d2_inc_en = 0;
      fb_r_pre = fb_r;
   end
end
//----------
assign out1 = channel_1;
assign out2 = channel_2;

endmodule

module delay123
   #(
      parameter delay1 = 8,
      parameter max_delay2 = 20
   ) (
    input wire clk,
    input wire reset,
    input wire fb_l,
    input wire fb_r,
    output reg ctrl = 0
  );

  localparam max_delay3 = max_delay2 - delay1;

  reg [7:0] delay2 = 0;
  reg [$clog2(max_delay2 + 1) - 1:0] delay2_cnt = 0;
  reg [$clog2(max_delay3 + 1) - 1:0] delay3_cnt = 0;
  reg fb_l_perv = 0;
  reg fb_r_perv = 0;
  reg fb_trig;

  always @(posedge clk) begin
    fb_l_perv <= fb_l;
    fb_r_perv <= fb_r;
    if (fb_l && !fb_l_perv) begin
      fb_trig <= 1'b1;
      delay2_cnt <= 2;
    end
    if (fb_r && !fb_r_perv) begin
      fb_trig <= 1'b0;
      delay2 <= delay2_cnt;
    end
    if (fb_trig) begin
      delay2_cnt <= delay2_cnt + 1'b1;
    end
  end

  always @(posedge clk) begin
    if (fb_l) begin
      if (delay3_cnt < delay2 - delay1) begin
        delay3_cnt <= delay3_cnt + 1'b1;
      end else begin
        ctrl <= 1'b1;
      end
    end else begin
      if (delay3_cnt > 0) begin
        delay3_cnt <= delay3_cnt - 1'b1;
      end else begin
        ctrl <= 1'b0;
      end
    end
  end
endmodule