void init(void) {
   DBGMCU->CR |= DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_DBG_STOP;
   RCC->AHBENR = RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOFEN | RCC_AHBENR_DMAEN | RCC_AHBENR_SRAMEN; // All GPIO + DMA, Enable SRAM during sleep mode.

<...>

   // ADC
   ADC1->CR = ADC_CR_ADCAL;      // Run calibration
   while (ADC1->CR & ADC_CR_ADCAL) {};   // Wait till done
   ADC1->CR = ADC_CR_ADEN;         // Enable ADC
   ADC1->SMPR = 4;            // 41.5 ADC clocks to aquire voltage
   delay_ms(2);
   ADC1->CR = ADC_CR_ADEN | ADC_CR_ADSTART;
   while ((ADC1->ISR & ADC_ISR_EOC) == 0) {};
   ADC_Value = (ADC1->DR * 1730) / 1000;
   
   // ADC DMA
   SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_ADC_DMA_RMP;
   DMA1_Channel1->CCR = DMA_CCR_PL_0 | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_MINC | DMA_CCR_TCIE;
   DMA1_Channel1->CPAR = (uint32_t)&(ADC1->DR);
   DMA1_Channel1->CNDTR = Len;
   DMA1_Channel1->CMAR = (uint32_t)&(Samples);
   NVIC_SetPriority(DMA1_Channel1_IRQn, 7);
   NVIC_EnableIRQ(DMA1_Channel1_IRQn);
   // TIM1 Update used as TRGO (Trigger Out)
   TIM1->CR2 = TIM_CR2_MMS_1;
   // 16MHz / 2500 = 6400Hz -> 80ms to 512 samples
   // 20MHz / 6400Hz = 3125 -1 = 3124, but... let it bee~ in run time.
   TIM1->ARR = (SystemCoreClock / 6400) - 1;
   TIM1->CR1 = TIM_CR1_ARPE | TIM_CR1_URS;
   // ----------


};


int main (void) {

<...>
   init();

   while (1) {
   <...> main loop code
// ----------
   ADC1->CR = ADC_CR_ADDIS;      // Disable ADC
   while (ADC1->CR & ADC_CR_ADEN) {};   // Wait till OFF
   ADC1->CFGR1 = ADC_CFGR1_EXTEN | ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_DISCEN;
   ADC1->CHSELR = (1 << 2);   // Channel 2 [Radio ADC]
   ADC1->CR = ADC_CR_ADEN;         // Enable ADC
   while (!(ADC1->ISR & ADC_ISR_ADRDY));   // Wait till ready.
   TIM1->CR1 |= TIM_CR1_CEN;
   ADC1->ISR = 0x1F;         // Clear flags.
   ADC1->CR = ADC_CR_ADSTART;      // Required!
   DMA1_Channel1->CNDTR = Len;
   DMA1_Channel1->CCR |= DMA_CCR_EN;
// ----------
   <...>
   __WFI();