void init (void)
{
  unsigned long HSEStatus;
  unsigned int StartUpCounter;

  // Clock setup
  RCC->CR |= RCC_CR_HSEON;            // HSE clock enable

  /* Wait till HSE is ready and if Time out is reached exit */
  StartUpCounter = 0;
  do
  {
    HSEStatus = (RCC->CR & RCC_CR_HSERDY);   // Выделение бита HSEREADY
    StartUpCounter++; 
  }
    while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if (RCC->CR & RCC_CR_HSERDY)   // if HSE is UP
  {
// USBCLK = 48MHz
    RCC->CFGR |= RCC_CFGR_USBPRE;       // USB prescaler = 1
// PLLCLK = 48MHz
    RCC->CFGR |= RCC_CFGR_PLLMULL6;     // PLL multiplication factor = 6
// HSE = 8 MHz
    RCC->CFGR |= RCC_CFGR_PLLSRC_HSE;   // HSE as PLL input clock
// AHB clock = 12 MHz
    RCC->CFGR |= RCC_CFGR_HPRE_DIV4;    // AHB prescaler = /4
    RCC->CFGR |= RCC_CFGR_MCO_PLL;      // MCO = PLLCLK/2

// APB high-speed prescaler (APB2) not divided (12 MHz).
    RCC->CFGR &= ~RCC_CFGR_PPRE2;
// APB low-speed prescaler (APB1) not divided (12 MHz).
    RCC->CFGR &= ~RCC_CFGR_PPRE1;   
// ADC prescaler, ADCCLK = APB2/6 = 2MHz
    RCC->CFGR |= RCC_CFGR_ADCPRE_DIV6;
// PLL enable
    RCC->CR |= RCC_CR_PLLON;
// Wait for PLL ready
    while((RCC->CR & RCC_CR_PLLRDY) == 0);   
// SYSCLK = 48 MHz
    RCC->CFGR |= RCC_CFGR_SW_PLL;       // System clock switch = PLL
// Wait PLL as system clock
    while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
  }
    else
    {
      // What to do if HSE failed.
      RCC->CR &= RCC_CR_HSEON;   // HSE oscillator OFF
      RCC->CR |= RCC_CR_HSION;   // Internal 8 MHz RC oscillator ON
      while((RCC->CR & RCC_CR_HSIRDY) == 0);   // Ожидание готовности HSI
      RCC->CFGR &= RCC_CFGR_PLLSRC_HSI_Div2;   // HSI/2 as PLL input clock
      RCC->CFGR |= RCC_CFGR_PLLMULL12;     // PLL multiplication factor = 12
    }
}

void t2set (void)
{
  // TIM2 clock enabled (12 MHz)
  RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
  // Counter used as downcounter:
  TIM2->CR1 = TIM_CR1_DIR;
  // Only counter overflow/underflow generates an update interrupt or DMA request if enabled:
  TIM2->CR1 |= TIM_CR1_URS;
  // Auto-reload preload enable (ARR)
  TIM2->CR1 |= TIM_CR1_ARPE;
  // Timer prescaler
  TIM2->PSC = 0x2EE0;     // 12000 * (1/12)us = 1ms = 1 Tick
  //TIM2->PSC = 12;           // 12 * (1/12)us = 1us = 1 Tick
  // Autoreload value
  TIM2->ARR = MS500 - 1;    // 500ms with 1ms tick
  //TIM2->ARR = 999;          // 1ms with 1us tick
  // Counter enabled:
  TIM2->CR1 |= TIM_CR1_CEN;
  // Initial value
  TIM2->DIER = 0;
  // Update interrupt enable:
  TIM2->DIER |= TIM_DIER_UIE;
  // Clear TIM2 flag
  TIM2->SR &= ~TIM_SR_UIF;
  // Interrupt enable:
  NVIC_EnableIRQ(TIM2_IRQn);
  // To freeze the Timer during debug when program pauses.
  DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP;
}