#define APP_BOOT_ADDRESS       (PA_TO_KVA0(0x1d097B00UL))
#define APP_START_ADDRESS       (PA_TO_KVA0(0x1d090000UL))
//----------
void run_Application()
{
    uint32_t msp            = *(uint32_t *)(APP_START_ADDRESS);

    void (*fptr)(void);

    /* Set default to APP_RESET_ADDRESS */
    fptr = (void (*)(void))APP_START_ADDRESS;

    if (msp == 0xffffffff)
    {
        return;
    }

    fptr();
}
//----------
void run_Boot()
{
    //uint32_t msp            = *(uint32_t *)(APP_BOOT_ADDRESS);
    UART1_Write_Text("  Flash_UPD");
    void (*fptr)(void);
    UART1_Write_Text("  Flash_UPD2");
    /* Set default to APP_RESET_ADDRESS */
    fptr = (void (*)(void))APP_BOOT_ADDRESS;
    UART1_Write_Text("  -3");
//    if (msp == 0xffffffff)
//    {
//        return;
//        UART1_Write_Text("  -4");
//    }
    UART1_Write_Text("  -5");
    fptr();
   
}
//=================
void main()
{
    Init();
    run_Boot(); // вместо бута, ресет  :)))
    // при попытке сделать тоже в буте, тоже ресет, где то что то я не дочитал
}

/* This code example illustrates the DMA channel 0 configuration for data transfer with pattern
    match enabled. Transfer from the UART1 a <CR> ended string, at most 200 characters long */
    IEC1CLR=0x00010000; // disable DMA channel 0 interrupts
    IFS1CLR=0x00010000; // clear any existing DMA channel 0 interrupt flag
    DMACONSET=0x00008000; // enable the DMA controller
    DCH0CON=0x03; // channel off, priority 3, no chaining
    DCH0ECON=(27 <<8)| 0x30; // start irq is UART1 RX, pattern match enabled
    DCH0DAT='\r'; // pattern value, carriage return
    // program the transfer
    DCH0SSA=KVA_TO_PA(&U2RXREG); // transfer source physical address
    DCH0DSA=KVA_TO_PA(ramBuff); // transfer destination physical address
    DCH0SSIZ=1; // source size is 1 byte
    DCH0DSIZ=200; // destination size at most 200 bytes
    DCH0CSIZ=1; // one byte per UART transfer request
    DCH0INTCLR=0x00ff00ff; // clear existing events, disable all interrupts
    DCH0INTSET=0x00090000; // enable Block Complete and error interrupts
    IPC9CLR=0x0000001f; // clear the DMA channel 0 priority and sub-priority
    IPC9SET=0x00000016; // set IPL 5, sub-priority 2
    IEC1SET=0x00010000; // enable DMA channel 0 interrupt
    DCH0CONSET=0x80; // turn channel on