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Код: Выделить всё

module summator (
input clock,
input button1, //+
input button2, //-
input button3, //<<
input button4, //>>
input button5, //

output reg[7:0] summa
);

always @(negedge button1 or posedge clock)
    begin
       summa = summa + 1;
    end

always @(negedge button2)
    begin
       summa = summa - 1;
    end

always @(negedge button3)
    begin
       summa = summa << 1;
    end

always @(negedge button4)
    begin
       summa = summa >> 1;
    end
endmodule

Код: Выделить всё

	always @(posedge clock)
	begin
		case (rstate)
			rWait:
			begin
				if (we)		// Wait until a new sample is written to memory
				begin
					rstate <= rAddr;
					counter <= NTAPS[ADDRBITS:0] + 1'd1;	// count samples and pipeline latency
					raddr <= waddr;		// read address -> newest sample
					caddr <= 1'd0;		// start at coefficient zero
					Raccum <= 1'd0;
					Iaccum <= 1'd0;
					Rmult <= 1'd0;
					Imult <= 1'd0;
				end
			end
			rAddr:	// prime the memory pipeline
			begin
				rstate <= rAddrA;
				next_addr;
			end
			rAddrA:
			begin
				rstate <= rAddrB;
				next_addr;
			end
			rAddrB:
			begin
				rstate <= rRun;
				next_addr;
			end
			rRun:
			begin		// main pipeline here
				next_addr;
				Rmult <= q_real * reg_coef;
				Imult <= q_imag * reg_coef;
				// Raccum <= Raccum + Rmult[MBITS*2-1 -: ABITS];
				// Iaccum <= Iaccum + Imult[MBITS*2-1 -: ABITS];
				// Correction by Phil, VK6APH, to remove DC spur
				Raccum <= Raccum + Rmult[MBITS*2-1 -: ABITS] + Rmult[MBITS*2-1-ABITS];
				Iaccum <= Iaccum + Imult[MBITS*2-1 -: ABITS] + Imult[MBITS*2-1-ABITS];
				counter <= counter - 1'd1;
				if (counter == 0)
					rstate <= rWait;
			end
		endcase
	end