Код: Выделить всё
#define DMA1_Channel_X DMA1_Channel3
DMA1_Channel_X->CCR |= DMA_CCR_MSIZE_0; // Memory size 16 bit
DMA1_Channel_X->CCR |= DMA_CCR_PSIZE_0; // Peripheral size 16 bit
DMA1_Channel_X->CCR |= DMA_CCR_PL_1; // Channel Priority level High
DMA1_Channel_X->CCR |= DMA_CCR_MINC; // Memory increment mode
DMA1_Channel_X->CCR |= DMA_CCR_CIRC; // Circular mode
DMA1_Channel_X->CCR |= DMA_CCR_DIR; // Data transfer direction Memory -> Peripheral
Код: Выделить всё
//csl.h (Chip Support Layer)
//------------
//DMA channel assignments
#define DMAREQ_S0_SPI3_RX 0
#define DMAREQ_S0_I2C1_RX 1
#define DMAREQ_S0_TIM4_CH1 2
#define DMAREQ_S0_I2S3_EXT_RX 3
#define DMAREQ_S0_UART5_RX 4
#define DMAREQ_S0_UART8_TX 5
#define DMAREQ_S0_TIM5_CH3 6
#define DMAREQ_S0_TIM5_UP 6
#define DMAREQ_S1_TIM2_CH3 3
#define DMAREQ_S1_TIM2_UP 3
#define DMAREQ_S1_UART3_RX 4
#define DMAREQ_S1_UART7_TX 5
#define DMAREQ_S1_TIM5_CH4 6
#define DMAREQ_S1_TIM5_TRIG 6
#define DMAREQ_S1_TIM6_UP 7
#define DMAREQ_S2_SPI3_RX 0
#define DMAREQ_S2_TIM7_UP 1
#define DMAREQ_S2_I2S3_EXT_RX 2
#define DMAREQ_S2_I2C3_RX 3
#define DMAREQ_S2_UART4_RX 4
#define DMAREQ_S2_TIM3_CH4 5
#define DMAREQ_S2_TIM3_UP 5
#define DMAREQ_S2_TIM5_CH1 6
#define DMAREQ_S2_I2C2_RX 7
#define DMAREQ_S3_SPI2_RX 0
#define DMAREQ_S3_TIM4_CH2 2
#define DMAREQ_S3_I2S2_EXT_RX 3
#define DMAREQ_S3_UART3_TX 4
#define DMAREQ_S3_UART7_RX 5
#define DMAREQ_S3_TIM5_CH4 6
#define DMAREQ_S3_TIM5_TRIG 6
#define DMAREQ_S3_I2C2_RX 7
#define DMAREQ_S4_SPI2_TX 0
#define DMAREQ_S4_TIM7_UP 1
#define DMAREQ_S4_I2S2_EXT_TX 2
#define DMAREQ_S4_I2C3_TX 3
#define DMAREQ_S4_UART4_TX 4
#define DMAREQ_S4_TIM3_CH1 5
#define DMAREQ_S4_TIM3_TRIG 5
#define DMAREQ_S4_TIM5_CH2 6
#define DMAREQ_S4_UART3_TX 7
#define DMAREQ_S5_SPI3_TX 0
#define DMAREQ_S5_I2C1_RX 1
#define DMAREQ_S5_I2S3_EXT_TX 2
#define DMAREQ_S5_TIM2_CH1 3
#define DMAREQ_S5_UART2_RX 4
#define DMAREQ_S5_TIM3_CH2 5
#define DMAREQ_S5_DAC0 7
#define DMAREQ_S6_I2C1_TX 1
#define DMAREQ_S6_TIM4_UP 2
#define DMAREQ_S6_TIM2_CH2 3
#define DMAREQ_S6_TIM2_CH4 3
#define DMAREQ_S6_UART2_TX 4
#define DMAREQ_S6_UART8_RX 5
#define DMAREQ_S6_TIM5_UP 6
#define DMAREQ_S6_DAC1 7
#define DMAREQ_S7_SPI3_TX 0
#define DMAREQ_S7_I2C1_TX 1
#define DMAREQ_S7_TIM4_CH3 2
#define DMAREQ_S7_TIM2_CH4 3
#define DMAREQ_S7_TIM2_UP 3
#define DMAREQ_S7_UART5_TX 4
#define DMAREQ_S7_TIM3_CH3 5
#define DMAREQ_S7_I2C2_TX 7
#define DMAREQ_S8_ADC1 0
#define DMAREQ_S8_ADC3 2
#define DMAREQ_S8_SPI1_RX 3
#define DMAREQ_S8_SPI4_RX 4
#define DMAREQ_S8_TIM1_TRIG 6
#define DMAREQ_S9_SAI1_A 0
#define DMAREQ_S9_DCMI 1
#define DMAREQ_S9_ADC3 2
#define DMAREQ_S9_SPI4_TX 4
#define DMAREQ_S9_UART6_RX 5
#define DMAREQ_S9_TIM1_CH1 6
#define DMAREQ_S9_TIM8_UP 7
#define DMAREQ_S10_TIM8_CH1 0
#define DMAREQ_S10_TIM8_CH2 0
#define DMAREQ_S10_TIM8_CH3 0
#define DMAREQ_S10_ADC2 1
#define DMAREQ_S10_SPI1_RX 3
#define DMAREQ_S10_UART1_RX 4
#define DMAREQ_S10_UART6_RX 5
#define DMAREQ_S10_TIM1_CH2 6
//#define DMAREQ_S10_TIM8_CH1 7
#define DMAREQ_S11_SAI1_A 0
#define DMAREQ_S11_ADC2 1
#define DMAREQ_S11_SPI5_RX 2
#define DMAREQ_S11_SPI1_TX 3
#define DMAREQ_S11_SDIO 4
#define DMAREQ_S11_SPI4_RX 5
#define DMAREQ_S11_TIM1_CH1 6
#define DMAREQ_S11_TIM8_CH2 7
#define DMAREQ_S12_ADC1 0
#define DMAREQ_S12_SAI1_B 1
#define DMAREQ_S12_SPI5_TX 2
#define DMAREQ_S12_SPI4_TX 5
#define DMAREQ_S12_TIM1_CH4 6
#define DMAREQ_S12_TIM1_TRIG 6
#define DMAREQ_S12_TIM1_COM 6
#define DMAREQ_S12_TIM8_CH3 7
#define DMAREQ_S13_SAI1_B 0
#define DMAREQ_S13_SPI6_TX 1
#define DMAREQ_S13_CRYP_OUT 2
#define DMAREQ_S13_SPI1_TX 3
#define DMAREQ_S13_UART1_RX 4
#define DMAREQ_S13_TIM1_UP 6
#define DMAREQ_S13_SPI5_RX 7
#define DMAREQ_S14_TIM1_CH1 0
#define DMAREQ_S14_TIM1_CH2 0
#define DMAREQ_S14_TIM1_CH3 0
#define DMAREQ_S14_SPI6_RX 1
#define DMAREQ_S14_CRYP_IN 2
#define DMAREQ_S14_SDIO 4
#define DMAREQ_S14_UART6_TX 5
//#define DMAREQ_S14_TIM1_CH3 6
#define DMAREQ_S14_SPI5_TX 7
#define DMAREQ_S15_DCMI 1
#define DMAREQ_S15_HASH_IN 2
#define DMAREQ_S15_UART1_TX 4
#define DMAREQ_S15_UART6_TX 5
#define DMAREQ_S15_TIM8_CH4 7
#define DMAREQ_S15_TIM8_TRIG 7
#define DMAREQ_S15_TIM8_COM 7
//board.h (распределение ресурсов платы)
//---------------------------------
//Распределение DMA-stream-ов
#define nDMASTR_UART1_TX 15
#define nDMASTR_UART1_RX 10
#define nDMASTR_UART5_TX 7
#define nDMASTR_UART5_RX 0
#define nDMASTR_UART6_TX 14
#define nDMASTR_UART6_RX 9
#define nDMASTR_SPI5_TX 12
#define nDMASTR_SPI5_RX 11
#define nDMASTR_SPI1_TX 13
#define nDMASTR_SPI1_RX 8
#define nDMASTR_I2C3_TX 4
#define nDMASTR_I2C3_RX 2
#define nDMASTR_DAC 5
//драйвер аудио-потока (aout.cpp):
//---------------------------------
#define dmaU ((nDMASTR_DAC >> 3) ? &DMA2: &DMA1)
#define dmaS (&dmaU->STREAM[nDMASTR_DAC & 7])
...
dmaS->CR = 1 << DMA_CR_EN | 1 << DMA_CR_TEIE | 1 << DMA_CR_TCIE |
1 << DMA_CR_DIR | 1 << DMA_CR_DBM | DMAPRI_DAC << DMA_CR_PL |
1 << DMA_CR_MINC | 2 << DMA_CR_PSIZE | 2 << DMA_CR_MSIZE |
concat(DMAREQ_S, nDMASTR_DAC, _DAC, concat(DAC_DMASTR, nDMASTR_DAC)) <<
DMA_CR_CHSEL;
Было бы лучше написать таким образом этот пример.dosikus писал(а):Это учебный пример для чего и комменты на манипуляции с каждым битом.
Код: Выделить всё
#define DMA1_Channel_X DMA1_Channel3
DMA1_Channel_X->CCR |= DMA_CCR_MSIZE_0 | // Memory size 16 bit
DMA_CCR_PSIZE_0 | // Peripheral size 16 bit
DMA_CCR_PL_1 | // Channel Priority level High
DMA_CCR_MINC | // Memory increment mode
DMA_CCR_CIRC | // Circular mode
DMA_CCR_DIR; // Data transfer direction Memory -> Peripheral
Потому что это не влияет на производительность, не об этом вам думать надо. Читаемость кода в варианте Досикуса лучше.jcxz писал(а): Никогда не понимал - на кой для каждого битового поля делать отдельное чтение-модификация-запись (LDR/ORR/STR) вместо просто записи всего слова сразу?
Код: Выделить всё
DMA1_Channel3->CCR = (
1 * DMA_CCR_EN | // Channel enable
1 * DMA_CCR_TCIE | // Transfer complete interrupt enable
0 * DMA_CCR_HTIE | // Half Transfer interrupt enable
1 * DMA_CCR_TEIE | // Transfer error interrupt enable
0 * DMA_CCR_DIR | // Data transfer direction
0 * DMA_CCR_CIRC | // Circular mode
0 * DMA_CCR_PINC | // Peripheral increment mode
1 * DMA_CCR_MINC | // Memory increment mode
// PSIZE[1:0] bits (Peripheral size)
// 00: 8-bits
// 01: 16-bits
// 10: 32-bits
// 11: Reserved
0 * DMA_CCR_PSIZE_1 | // Bit 1
0 * DMA_CCR_PSIZE_0 | // Bit 0
// MSIZE[1:0] bits (Memory size)
// 00: 8-bits
// 01: 16-bits
// 10: 32-bits
// 11: Reserved
0 * DMA_CCR_MSIZE_0 | // Bit 0
0 * DMA_CCR_MSIZE_1 | // Bit 1
// PL[1:0] bits(Channel Priority level)
// 00: Low
// 01: Medium
// 10: High
// 11: Very high
0 * DMA_CCR_PL_0 | // Bit 0
1 * DMA_CCR_PL_1 | // Bit 1
0 * DMA_CCR_MEM2MEM // Memory to memory mode
);
