Project Information              c:\maxplus2\project\oscillog\ramdrive17_1.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/19/2008 21:18:47

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

ramdrive17_1
      EPM3064ATC100-10     8        20       0      24      20          37 %

User Pins:                 8        20       0  



Project Information              c:\maxplus2\project\oscillog\ramdrive17_1.rpt

** FILE HIERARCHY **



|lpm_counter:16|


Device-Specific Information:     c:\maxplus2\project\oscillog\ramdrive17_1.rpt
ramdrive17_1

***** Logic for device 'ramdrive17_1' compiled without errors.




Device: EPM3064ATC100-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffffffff
    MultiVolt I/O                              = OFF

                                                                    
                                                                    
                                                                    
                   R R R R   R R R                                  
                 1 E E E E   E E E               c       o          
                 2 S S S S   S S S V             l       e          
                 8 E E E E   E E E C           a k   V   _ a     a  
                 / R R R R   R R R C           d _ a C a r d   N d  
                 1 V V V V G V V V I G G G G G r r d C d a r G . r  
                 k E E E E N E E E N N N N N N 1 a r I r m 1 N C 1  
                 b D D D D D D D D T D D D D D 3 m 8 O 9 _ 6 D . 5  
               ----------------------------------------------------_ 
              / 100  98  96  94  92  90  88  86  84  82  80  78  76   |_ 
             /     99  97  95  93  91  89  87  85  83  81  79  77    | 
       N.C. |  1                                                    75 | adr12 
       N.C. |  2                                                    74 | GND 
      VCCIO |  3                                                    73 | #TDO 
       #TDI |  4                                                    72 | N.C. 
       N.C. |  5                                                    71 | adr14 
   trig_rec |  6                                                    70 | N.C. 
       N.C. |  7                                                    69 | adr11 
  en_oe_ram |  8                                                    68 | adr10 
 read_count |  9                                                    67 | adr7 
        rec | 10                                                    66 | VCCIO 
        GND | 11                                                    65 | GND 
  Rec_count | 12                                                    64 | adr6 
reset_count | 13                 EPM3064ATC100-10                   63 | ready_we_ 
     d_sync | 14                                                    62 | #TCK 
       #TMS | 15                                                    61 | RESERVED 
   RESERVED | 16                                                    60 | RESERVED 
   RESERVED | 17                                                    59 | GND 
      VCCIO | 18                                                    58 | RESERVED 
   RESERVED | 19                                                    57 | RESERVED 
   RESERVED | 20                                                    56 | RESERVED 
   RESERVED | 21                                                    55 | N.C. 
       N.C. | 22                                                    54 | RESERVED 
   RESERVED | 23                                                    53 | GND 
       N.C. | 24                                                    52 | RESERVED 
   RESERVED | 25                                                    51 | VCCIO 
            |      27  29  31  33  35  37  39  41  43  45  47  49  _| 
             \   26  28  30  32  34  36  38  40  42  44  46  48  50   | 
              \----------------------------------------------------- 
                 G N N R R R R G V R R R G V a a a G a a a R R N N  
                 N . . E E E E N C E E E N C d d d N d d d E E . .  
                 D C C S S S S D C S S S D C r r r D r r r S S C C  
                   . . E E E E   I E E E   I 0 4 3   1 2 5 E E . .  
                       R R R R   O R R R   N               R R      
                       V V V V     V V V   T               V V      
                       E E E E     E E E                   E E      
                       D D D D     D D D                   D D      
                                                                    
                                                                    
                                                                    


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:     c:\maxplus2\project\oscillog\ramdrive17_1.rpt
ramdrive17_1

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   9/16( 56%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     0/16(  0%)   1/15(  6%)   0/16(  0%)   0/36(  0%) 
C:    LC33 - LC48     8/16( 50%)   7/16( 43%)  11/16( 68%)  17/36( 47%) 
D:    LC49 - LC64    16/16(100%)  15/15(100%)  11/16( 68%)  27/36( 75%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            32/62     ( 51%)
Total logic cells used:                         24/64     ( 37%)
Total shareable expanders used:                 20/64     ( 31%)
Total Turbo logic cells used:                   24/64     ( 37%)
Total shareable expanders not available (n/a):   2/64     (  3%)
Average fan-in:                                  11.58
Total fan-in:                                   278

Total input pins required:                       8
Total output pins required:                     20
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     24
Total flipflops required:                       20
Total product terms required:                   95
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          18

Synthesized logic cells:                         2/  64   (  3%)



Device-Specific Information:     c:\maxplus2\project\oscillog\ramdrive17_1.rpt
ramdrive17_1

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  14    (1)  (A)      INPUT               0      0   0    0    0    1    1  d_sync
   8    (6)  (A)      INPUT               0      0   0    0    0    1    0  en_oe_ram
   9    (5)  (A)      INPUT               0      0   0    0    0   17    1  read_count
  10    (4)  (A)      INPUT               0      0   0    0    0    1    3  rec
  12    (3)  (A)      INPUT               0      0   0    0    0   17    1  Rec_count
  13    (2)  (A)      INPUT               0      0   0    0    0   17    1  reset_count
   6    (7)  (A)      INPUT               0      0   0    0    0    0    1  trig_rec
 100    (9)  (A)      INPUT               0      0   0    0    0    1    2  128/1kb


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:     c:\maxplus2\project\oscillog\ramdrive17_1.rpt
ramdrive17_1

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  40     33    C         FF      t        2      2   0    3    1   18    1  adr0
  44     36    C         FF      t        2      2   0    3    2   16    1  adr1
  45     37    C         FF      t        2      2   0    3    3   15    1  adr2
  42     35    C         FF      t        2      2   0    3    4   14    1  adr3
  41     34    C         FF      t        2      2   0    3    5   13    1  adr4
  46     38    C         FF      t        2      2   0    3    6   12    1  adr5
  64     50    D         FF      t        2      2   0    3    7   11    1  adr6
  67     52    D         FF      t        2      2   0    3    8   10    1  adr7
  83     62    D         FF      t        2      2   0    3    9    9    1  adr8
  81     61    D         FF      t        2      2   0    3   10    8    1  adr9
  68     53    D         FF      t        2      2   0    3   11    7    1  adr10
  69     54    D         FF      t        2      2   0    3   12    6    1  adr11
  75     57    D         FF      t        2      2   0    3   13    5    1  adr12
  85     64    D         FF      t        2      2   0    3   14    4    1  adr13
  71     55    D         FF      t        2      2   0    3   15    3    1  adr14
  76     58    D         FF      t        2      2   0    3   16    2    1  adr15
  79     59    D         FF      t        2      2   0    3   17    1    1  adr16
  84     63    D     OUTPUT      t        0      0   0    0    2    0    0  clk_ram
  80     60    D     OUTPUT      t        0      0   0    1    1    0    0  oe_ram_
  63     49    D         FF      t !      7      0   0    3   18   18    1  ready_we_


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:     c:\maxplus2\project\oscillog\ramdrive17_1.rpt
ramdrive17_1

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (47)    39    C       DFFE      t        7      0   0    3   10    1    1  :28
   -     51    D       SOFT    s t        1      0   1    2    5    0    1  ~31~1
 (73)    56    D       SOFT    s t        1      0   1    2    5    0    1  ~31~2
 (48)    40    C       TFFE      t        2      0   0    3    1    1    0  :45


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:     c:\maxplus2\project\oscillog\ramdrive17_1.rpt
ramdrive17_1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                         Logic cells placed in LAB 'C'
        +--------------- LC33 adr0
        | +------------- LC36 adr1
        | | +----------- LC37 adr2
        | | | +--------- LC35 adr3
        | | | | +------- LC34 adr4
        | | | | | +----- LC38 adr5
        | | | | | | +--- LC39 :28
        | | | | | | | +- LC40 :45
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC33 -> * * * * * * * - | - - * * | <-- adr0
LC36 -> - * * * * * * - | - - * * | <-- adr1
LC37 -> - - * * * * * - | - - * * | <-- adr2
LC35 -> - - - * * * * - | - - * * | <-- adr3
LC34 -> - - - - * * * - | - - * * | <-- adr4
LC38 -> - - - - - * * - | - - * * | <-- adr5
LC39 -> - - - - - - * - | - - * * | <-- :28

Pin
14   -> - - - - - - * - | - - * * | <-- d_sync
9    -> * * * * * * - * | - - * * | <-- read_count
10   -> - - - - - - * - | - - * * | <-- rec
12   -> * * * * * * - * | - - * * | <-- Rec_count
13   -> * * * * * * - * | - - * * | <-- reset_count
6    -> - - - - - - * - | - - * - | <-- trig_rec
LC50 -> - - - - - - * - | - - * * | <-- adr6
LC49 -> * * * * * * - * | - - * * | <-- ready_we_
LC51 -> - - - - - - * - | - - * - | <-- ~31~1
LC56 -> - - - - - - * - | - - * - | <-- ~31~2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:     c:\maxplus2\project\oscillog\ramdrive17_1.rpt
ramdrive17_1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC50 adr6
        | +----------------------------- LC52 adr7
        | | +--------------------------- LC62 adr8
        | | | +------------------------- LC61 adr9
        | | | | +----------------------- LC53 adr10
        | | | | | +--------------------- LC54 adr11
        | | | | | | +------------------- LC57 adr12
        | | | | | | | +----------------- LC64 adr13
        | | | | | | | | +--------------- LC55 adr14
        | | | | | | | | | +------------- LC58 adr15
        | | | | | | | | | | +----------- LC59 adr16
        | | | | | | | | | | | +--------- LC63 clk_ram
        | | | | | | | | | | | | +------- LC60 oe_ram_
        | | | | | | | | | | | | | +----- LC49 ready_we_
        | | | | | | | | | | | | | | +--- LC51 ~31~1
        | | | | | | | | | | | | | | | +- LC56 ~31~2
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC50 -> * * * * * * * * * * * - - * - - | - - * * | <-- adr6
LC52 -> - * * * * * * * * * * - - * - * | - - - * | <-- adr7
LC62 -> - - * * * * * * * * * - - * - * | - - - * | <-- adr8
LC61 -> - - - * * * * * * * * - - * - * | - - - * | <-- adr9
LC53 -> - - - - * * * * * * * - - * - * | - - - * | <-- adr10
LC54 -> - - - - - * * * * * * - - * - * | - - - * | <-- adr11
LC57 -> - - - - - - * * * * * - - * * - | - - - * | <-- adr12
LC64 -> - - - - - - - * * * * - - * * - | - - - * | <-- adr13
LC55 -> - - - - - - - - * * * - - * * - | - - - * | <-- adr14
LC58 -> - - - - - - - - - * * - - * * - | - - - * | <-- adr15
LC59 -> - - - - - - - - - - * - - * * - | - - - * | <-- adr16
LC49 -> * * * * * * * * * * * - * - - - | - - * * | <-- ready_we_

Pin
14   -> - - - - - - - - - - - - - * - - | - - * * | <-- d_sync
8    -> - - - - - - - - - - - - * - - - | - - - * | <-- en_oe_ram
9    -> * * * * * * * * * * * - - - - - | - - * * | <-- read_count
10   -> - - - - - - - - - - - - - * * * | - - * * | <-- rec
12   -> * * * * * * * * * * * - - - - - | - - * * | <-- Rec_count
13   -> * * * * * * * * * * * - - - - - | - - * * | <-- reset_count
100  -> - - - - - - - - - - - - - * * * | - - - * | <-- 128/1kb
LC33 -> * * * * * * * * * * * * - * - - | - - * * | <-- adr0
LC36 -> * * * * * * * * * * * - - * - - | - - * * | <-- adr1
LC37 -> * * * * * * * * * * * - - * - - | - - * * | <-- adr2
LC35 -> * * * * * * * * * * * - - * - - | - - * * | <-- adr3
LC34 -> * * * * * * * * * * * - - * - - | - - * * | <-- adr4
LC38 -> * * * * * * * * * * * - - * - - | - - * * | <-- adr5
LC39 -> - - - - - - - - - - - - - * - - | - - * * | <-- :28
LC40 -> - - - - - - - - - - - * - - - - | - - - * | <-- :45


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:     c:\maxplus2\project\oscillog\ramdrive17_1.rpt
ramdrive17_1

** EQUATIONS **

d_sync   : INPUT;
en_oe_ram : INPUT;
read_count : INPUT;
rec      : INPUT;
Rec_count : INPUT;
reset_count : INPUT;
trig_rec : INPUT;
128/1kb  : INPUT;

-- Node name is 'adr0' = '|LPM_COUNTER:16|dffs0' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr0', type is output 
 adr0    = TFFE( VCC,  _EQ001, !reset_count,  VCC,  VCC);
  _EQ001 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr1' = '|LPM_COUNTER:16|dffs1' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr1', type is output 
 adr1    = TFFE( adr0,  _EQ002, !reset_count,  VCC,  VCC);
  _EQ002 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr2' = '|LPM_COUNTER:16|dffs2' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr2', type is output 
 adr2    = TFFE( _EQ003,  _EQ004, !reset_count,  VCC,  VCC);
  _EQ003 =  adr0 &  adr1;
  _EQ004 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr3' = '|LPM_COUNTER:16|dffs3' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr3', type is output 
 adr3    = TFFE( _EQ005,  _EQ006, !reset_count,  VCC,  VCC);
  _EQ005 =  adr0 &  adr1 &  adr2;
  _EQ006 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr4' = '|LPM_COUNTER:16|dffs4' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr4', type is output 
 adr4    = TFFE( _EQ007,  _EQ008, !reset_count,  VCC,  VCC);
  _EQ007 =  adr0 &  adr1 &  adr2 &  adr3;
  _EQ008 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr5' = '|LPM_COUNTER:16|dffs5' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr5', type is output 
 adr5    = TFFE( _EQ009,  _EQ010, !reset_count,  VCC,  VCC);
  _EQ009 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4;
  _EQ010 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr6' = '|LPM_COUNTER:16|dffs6' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr6', type is output 
 adr6    = TFFE( _EQ011,  _EQ012, !reset_count,  VCC,  VCC);
  _EQ011 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5;
  _EQ012 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr7' = '|LPM_COUNTER:16|dffs7' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr7', type is output 
 adr7    = TFFE( _EQ013,  _EQ014, !reset_count,  VCC,  VCC);
  _EQ013 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6;
  _EQ014 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr8' = '|LPM_COUNTER:16|dffs8' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr8', type is output 
 adr8    = TFFE( _EQ015,  _EQ016, !reset_count,  VCC,  VCC);
  _EQ015 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6 &  adr7;
  _EQ016 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr9' = '|LPM_COUNTER:16|dffs9' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr9', type is output 
 adr9    = TFFE( _EQ017,  _EQ018, !reset_count,  VCC,  VCC);
  _EQ017 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6 &  adr7 & 
              adr8;
  _EQ018 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr10' = '|LPM_COUNTER:16|dffs10' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr10', type is output 
 adr10   = TFFE( _EQ019,  _EQ020, !reset_count,  VCC,  VCC);
  _EQ019 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6 &  adr7 & 
              adr8 &  adr9;
  _EQ020 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr11' = '|LPM_COUNTER:16|dffs11' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr11', type is output 
 adr11   = TFFE( _EQ021,  _EQ022, !reset_count,  VCC,  VCC);
  _EQ021 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6 &  adr7 & 
              adr8 &  adr9 &  adr10;
  _EQ022 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr12' = '|LPM_COUNTER:16|dffs12' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr12', type is output 
 adr12   = TFFE( _EQ023,  _EQ024, !reset_count,  VCC,  VCC);
  _EQ023 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6 &  adr7 & 
              adr8 &  adr9 &  adr10 &  adr11;
  _EQ024 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr13' = '|LPM_COUNTER:16|dffs13' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr13', type is output 
 adr13   = TFFE( _EQ025,  _EQ026, !reset_count,  VCC,  VCC);
  _EQ025 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6 &  adr7 & 
              adr8 &  adr9 &  adr10 &  adr11 &  adr12;
  _EQ026 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr14' = '|LPM_COUNTER:16|dffs14' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr14', type is output 
 adr14   = TFFE( _EQ027,  _EQ028, !reset_count,  VCC,  VCC);
  _EQ027 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6 &  adr7 & 
              adr8 &  adr9 &  adr10 &  adr11 &  adr12 &  adr13;
  _EQ028 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr15' = '|LPM_COUNTER:16|dffs15' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr15', type is output 
 adr15   = TFFE( _EQ029,  _EQ030, !reset_count,  VCC,  VCC);
  _EQ029 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6 &  adr7 & 
              adr8 &  adr9 &  adr10 &  adr11 &  adr12 &  adr13 &  adr14;
  _EQ030 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'adr16' = '|LPM_COUNTER:16|dffs16' from file "lpm_counter.tdf" line 220, column 8
-- Equation name is 'adr16', type is output 
 adr16   = TFFE( _EQ031,  _EQ032, !reset_count,  VCC,  VCC);
  _EQ031 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6 &  adr7 & 
              adr8 &  adr9 &  adr10 &  adr11 &  adr12 &  adr13 &  adr14 & 
              adr15;
  _EQ032 =  _X001 &  _X002;
  _X001  = EXP(!read_count &  ready_we_);
  _X002  = EXP(!ready_we_ & !Rec_count);

-- Node name is 'clk_ram' 
-- Equation name is 'clk_ram', location is LC063, type is output.
 clk_ram = LCELL( _LC040 $  adr0);

-- Node name is 'oe_ram_' 
-- Equation name is 'oe_ram_', location is LC060, type is output.
 oe_ram_ = LCELL( _EQ033 $  VCC);
  _EQ033 =  en_oe_ram &  ready_we_;

-- Node name is 'ready_we_' = ':2' 
-- Equation name is 'ready_we_', type is output 
ready_we_ = _LC049~NOT;
_LC049~NOT = DFFE( VCC $  VCC,  _EQ034, !rec, !_EQ035,  VCC);
  _EQ034 =  d_sync &  _LC039;
  _EQ035 =  adr0 &  adr1 &  adr2 &  adr3 &  adr4 &  adr5 &  adr6 &  adr7 & 
              adr8 &  adr9 &  _X003 &  _X004 &  _X005 &  _X006 &  _X007 & 
              _X008 &  _X009;
  _X003  = EXP(!adr16 &  128/1kb);
  _X004  = EXP(!adr15 &  128/1kb);
  _X005  = EXP(!adr14 &  128/1kb);
  _X006  = EXP(!adr13 &  128/1kb);
  _X007  = EXP(!adr12 &  128/1kb);
  _X008  = EXP(!adr11 &  128/1kb);
  _X009  = EXP(!adr10 &  128/1kb);

-- Node name is ':28' 
-- Equation name is '_LC039', type is buried 
_LC039   = DFFE( GND $  GND,  _EQ036, !_EQ037, !trig_rec,  VCC);
  _EQ036 =  d_sync &  _LC039;
  _EQ037 = !_LC051 & !_LC056 &  _X010 &  _X011 &  _X012 &  _X013 &  _X014 & 
              _X015 &  _X016;
  _X010  = EXP(!adr6 & !rec);
  _X011  = EXP(!adr5 & !rec);
  _X012  = EXP(!adr4 & !rec);
  _X013  = EXP(!adr3 & !rec);
  _X014  = EXP(!adr2 & !rec);
  _X015  = EXP(!adr1 & !rec);
  _X016  = EXP(!adr0 & !rec);

-- Node name is '~31~1' 
-- Equation name is '~31~1', location is LC051, type is buried.
-- synthesized logic cell 
_LC051   = LCELL( _EQ038 $  GND);
  _EQ038 = !adr16 & !rec &  128/1kb
         # !adr15 & !rec &  128/1kb
         # !adr14 & !rec &  128/1kb
         # !adr13 & !rec &  128/1kb
         # !adr12 & !rec &  128/1kb;

-- Node name is '~31~2' 
-- Equation name is '~31~2', location is LC056, type is buried.
-- synthesized logic cell 
_LC056   = LCELL( _EQ039 $  GND);
  _EQ039 = !adr11 & !rec &  128/1kb
         # !adr10 & !rec &  128/1kb
         # !adr9 & !rec
         # !adr8 & !rec
         # !adr7 & !rec;

-- Node name is ':45' 
-- Equation name is '_LC040', type is buried 
_LC040   = TFFE( VCC,  _EQ040, !reset_count,  VCC,  VCC);
  _EQ040 =  _X017 &  _X018;
  _X017  = EXP( read_count &  ready_we_);
  _X018  = EXP(!ready_we_ &  Rec_count);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs C, D
--    _X002 occurs in LABs C, D




Project Information              c:\maxplus2\project\oscillog\ramdrive17_1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX3000A' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,684K
