.include "d:\UC\avr\avrasm\appnotes\2313def.inc"


	.def	Temp1=R16
	.def	Temp2=R17
	.def	Temp3=R18
	.def	Temp4=R19
	.def	Temp=R20


.dseg

Output:	.byte 10



;******************************************************************************
.macro	stsi		;save_immediate <SRAM_cell>,<k>
	ldi Temp,@1
	sts @0,Temp
.endmacro

.macro	sti		;save_immediate <SRAM_cell>,<k>
	ldi Temp,@1
	st @0,Temp
.endmacro

.macro	outi
	ldi Temp,@1
	out @0,Temp
.endmacro

.macro	rdm
	ldi ZH,High(@0*2)
	ldi ZL,Low(@0*2)
	add ZL,Temp1
	adc ZH,Temp2
	lpm
	mov Temp3,r0
.endmacro


;******************************************************************************

.cseg
.org 0

              rjmp RESET    ; Reset Handler
	rjmp EXT_INT0 ; IRQ0 Handler
	rjmp EXT_INT1 ; IRQ1 Handler
	rjmp TIM_CAPT1 ; Timer1 Capture Handler
	rjmp TIM_COMP1 ; Timer1 Compare Handler
	rjmp TIM_OVF1 ; Timer1 Overflow Handler
	rjmp TIM_OVF0 ; Timer0 Overflow Handler
	rjmp UART_RXC ; UART RX Complete Handler
	rjmp UART_DRE ; UDR Empty Handler
	rjmp UART_TXC ; UART TX Complete Handler
	rjmp ANA_COMP ; Analog Comparator Handler



EXT_INT0  :	ret
EXT_INT1  :	ret
TIM_CAPT1 :	ret
TIM_OVF0  :	ret
TIM_OVF1  :   ret
UART_RXC  :   ret
UART_DRE  :   ret
UART_TXC  :   ret
ANA_COMP  :   ret
TIM_COMP1 :   ret



reset:	ldi Temp1,RamEnd	;set stack
	out SPL,Temp1

	cli

	outi DDRB,0b01111111
	outi DDRD,0b00111100


	ldi YL,Low(Output)
	ldi YH,High(Output)

	sti Y+,0b00111011;g0
	sti Y+,0b00101110;r0
	sti Y+,0b00111011;g1
	sti Y+,0b00101110;r1
	sti Y+,0b00111011;g2
	sti Y+,0b00101110;r2
	sti Y+,0b00111011;g3
	sti Y+,0b00101110;r3
	sti Y+,0b00111011;g4
	sti Y, 0b00101110;r4



new_indicate:	ldi Temp4,0b01111111
	ldi Temp1,0
	ldi Temp2,0
	ldi Temp3,0b00000100
	ldi XL,Low(Output)
	ldi XH,High(Output)


indicate:	ld Temp,X+
`	eor Temp,Temp4
	out PortD,Temp2
	out PortB,Temp
	rcall DelayGreen
	inc Temp1
	add Temp2,Temp3

	ld Temp,X+
	eor Temp,Temp4
	out PortD,Temp2
	out PortB,Temp
	rcall DelayRed
	inc Temp1
	add Temp2,Temp3
	cpi Temp1,10
	brne indicate
	rjmp new_indicate


;**********************************************************************
DelayRed:
	push Temp1
	push Temp2


del1_main:	ldi Temp1,0
	ldi Temp2,5


d11:	dec Temp1
	brne d11

	dec Temp2
	brne d11


	pop Temp2
	pop Temp1

              ret



DelayGreen:
	push Temp1
	push Temp2


	ldi Temp1,0
	ldi Temp2,25

d22:

d21:	dec Temp1
	brne d21

	dec Temp2
	brne d21


	pop Temp2
	pop Temp1

              ret