FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;

      if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL)  /* (1) */
         {
          RCC->CFGR &= (uint32_t) (~RCC_CFGR_SW); /* (2) */
          while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) /* (3) */
          {
          /* For robust implementation, add here time-out management */
          }
         }
         
         RCC->CR &= (uint32_t)(~RCC_CR_PLLON); /* (4) */
         while((RCC->CR & RCC_CR_PLLRDY) != 0) /* (5) */
         {
          /* For robust implementation, add here time-out management */
         }
         
         RCC->CR |= RCC_CR_HSEON;                    // Включить HSE
      while((RCC->CR & RCC_CR_HSERDY) == 0) {}    // Ждём включения HSE

      //RCC->CFGR2 |= RCC_CFGR2_PREDIV1_DIV1;       // Предделитель PLL отключён
      RCC->CFGR |= RCC_CFGR_PLLSRC_HSE_PREDIV;    // Используем HSE для PLL
         
         
         FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
         
         RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_PLLMUL)) | (RCC_CFGR_PLLMUL6); /* (6) */
         RCC->CR |= RCC_CR_PLLON; /* (7) */
         while((RCC->CR & RCC_CR_PLLRDY) == 0) /* (8) */
         {
          /* For robust implementation, add here time-out management */
         }
         RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL); /* (9) */
         while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)  /* (10) */
         {
          /* For robust implementation, add here time-out management */
         }
         }

static void SetSysClock(void)
{
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  /* SYSCLK, HCLK, PCLK configuration ----------*/
  /* Enable HSE */
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
    StartUpCounter++;
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  {
    HSEStatus = (uint32_t)0x01;
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
  }

  if (HSEStatus == (uint32_t)0x01)
  {
    /* Enable Prefetch Buffer and set Flash Latency */
    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;

    /* HCLK = SYSCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

    /* PCLK = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;

    /* PLL configuration = HSE * 6 = 48 MHz */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);

    /* Enable PLL */
    RCC->CR |= RCC_CR_PLLON;

    /* Wait till PLL is ready */
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
    {
    }

    /* Select PLL as system clock source */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

    /* Wait till PLL is used as system clock source */
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
    {
    }
  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock
         configuration. User can add here some code to deal with this error */
  }
}