void rtc_init(void)
{
  // RTC setup
  // Power interface clock enable
  RCC->APB1ENR |= RCC_APB1ENR_PWREN;
  // Backup interface clock enabled
  RCC->APB1ENR |= RCC_APB1ENR_BKPEN;
  // Access to RTC and Backup registers enabled
  PWR->CR |= PWR_CR_DBP;
  // RTC clock enabled
  RCC->BDCR |= RCC_BDCR_RTCEN;
  // LSE clock as RTC
  RCC->BDCR |= RCC_BDCR_RTCSEL_0;
  RCC->BDCR &= ~RCC_BDCR_RTCSEL_1;
/*************************** RTC reg conf *********************************/
  // 1. Wait until the last write operation on RTC registers terminated.
  while((RTC->CRL & RTC_CRL_RTOFF) == 0);
  // 2. Enter configuration mode
  RTC->CRL |= RTC_CRL_CNF;
  /* 3. Set prescalaer
  * fTR_CLK = fRTCCLK/(PRL[19:0]+1),
  * where fRTCCLK = input frequency, fTR_CLK - output frequency. */
  RTC->PRLH = 0;
  RTC->PRLL = 0x7FFF;   // 1Hz (1.0s period).
  // 4. Exit configuration mode.
  RTC->CRL &= ~RTC_CRL_CNF;
  // 5. Wait until write operation on RTC registers terminated.
  while((RTC->CRL & RTC_CRL_RTOFF) == 0);
/**********************************************************************/
  // Overflow interrupt enable
  // RTC->CRH |= RTC_CRH_OWIE;
  // Alarm interrupt enable
  RTC->CRH |= RTC_CRH_ALRIE;
  // Second interrupt enable
  RTC->CRH |= RTC_CRH_SECIE;
  // LSE enabled
  RCC->BDCR |= RCC_BDCR_LSEON;
  // Wait until LSE is ready
  while((RCC->BDCR & RCC_BDCR_LSERDY) == 0);
  NVIC_EnableIRQ(RTC_IRQn);
}